1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor component provided with one or more conductive structural elements having the characteristics of the generic portion of patent claim 1 as well as to a semiconductor element provided with one or more structural elements which may be fabricated by such a method. More particularly, the present invention relates to a method of fabricating a metallized semiconductor circuit structure which may be practiced with CMOS-compatible standard semiconductor technologies and which complicates the use of so-called reverse engineering for the appropriation of foreign technology knowhow or for the selection and/or manipulation of data stored in the component.
2. The Prior Art
A method incorporating the characteristics of the generic portion of patent claim 1 is known, for instance, from G. Schumiki, P. Seegebrecht "Proze.beta.technologie", Springer-Verlag, Berlin, ISBN 3-540-17670-5. FIG. 5 shows a semiconductor component fabricated by such a method. In FIG. 5, the layers identified by reference numeral 12 are conductive layers built-up, for instance, of doped semiconductor material or of doped polysilicon layers, and the layers identified by reference numeral 13 are metallizations. Wiring 13 of the component is realized by depositing and structuring metal layers and intermediate insulation layers 11. In this modular method via holes are etched through an insulation layer 11 to a conductive structure 12, 13, followed by precipitation of a metall layer and subsequent structuring of conductor runs 13 and covering by a further insulation layer 11.
The problems inherent in such semiconductor components are, on the one hand, that the design and arrangement of the conductor runs within the component can be easily identified by reverse engineering techniques and that the method of fabricating such a semiconductor component can easily by forged by third parties.
For instance, semiconductor components can be optically radiographed, and their design can be easily "seen through" by electron beam microscopy utilizing either imaging methods or by tracing a flowing current. It is also customary mechanically or chemically to remove layer after layer of a semiconductor component and then to examine every resulting surface.
Taking into consideration the enormous development costs of novel semiconductor chips, it is clear that there exists a great need for ways of curtailing the likelihood of success of such reverse engineering methods.
A further problem resides in the fact that the utilization of such semiconductor components in chip cards opens the possibility of manipulation by third parties, which significantly lowers the security of chip cards. It is possible, for instance, by special techniques to read or alter, as the case may be, the data stored in the chip cards.
Steps hitherto taken for avoiding the problems mentioned supra consist, for instance, in improving the used PIN codes by the application of a secret number with an increased number of digits, in order to prevent unauthorized use of chip cards.
Attempts to solve the problem connected with reverse engineering methods seek to structure the design of chip cards as complicated as possible in order to reduce the possibilities of success of the previously mentioned optical penetration or electron microscopy methods. However, attempts of structuring a circuit to be fabricated in as complicated a manner as possible may lead to the problem of a markedly reduced level of integration of the circuit and that the fabrication process becomes technologically complex. More specifically, the level of integration may be enhanced by arranging several metallization planes in superposition. Because of the surface topography this does, however, also require an adaptation to given sizes of the circuit runs which results in a deterioration of the integration density of the metallization in the corresponding device.
Moreover, from U.S. Pat. No. 5,563,084, corresponding to German Patent 44 33 845 there is known a method of fabricating a three-dimensional integrated circuit. In accordance with this method, using a handling substrate fully processed chips are applied to a further substrate which may also contain several layers of components. To increase yield, the functioning of individual chips is tested before they are assembled.